Talk at EEAI2023

Abstract

The lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. We present SENECA, a digital neuromorphic architecture that balances the trade-offs between flexibility and efficiency using a hierarchical-controlling system. A SENECA core contains two controllers: a flexible RISC-V-based controller and an optimized controller (Loop Buffer). This flexible computational pipeline allows for deploying efficient mapping for various neural networks, on-device learning, and pre-post processing algorithms. The hierarchical-controlling system introduced in SENECA makes it one of the most efficient neuromorphic processors for event-driven neural network processing. In this talk, I will present the components of event-based neural network processing on SENECA, including detailed design space explorations and the optimized event-driven depth-first convolution. Further, I will present the benchmarking results on SENECA compared with state-of-the-art neuromorphic solutions and discuss how the research can benefit the future evolution of neuromorphic computing.

Guangzhi Tang

Researcher

My research interests include neuromorphic and brain-inspired AI and their applications in real-world problems.